Present dynamic random access memory (DRAM) technology uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor." One of the materials used is silicon, which is used as either single crystal silicon, amorphous silicon, or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
The memory cell typically stores a high logic level, "1," or a low logic level, "0." Since the memory cell utilizes a capacitor to store a charge representing the logic level, there is a possibility of leakage as a result of the capacitor discharging. There is no leakage associated with the low logic level since there is not a potential available to charge the cell to a higher potential. In contrast, when a high logic level is stored, leakage will eventually reduce the charge stored on the capacitor to a low logic level. A constant refresh is typically utilized to restore the high logic level.
In the operation of certain semiconductor circuit devices, such as dynamic random access memories (DRAMs), it is necessary to draw down the latch node (or the sense node) of the sense amplifier to a certain low potential, for example, a potential of V.sub.SS or V.sub.TN. The biasing of this node enables the sense amplifier to sense a differential in potentials between potential sources, such as between digit and digit* lines (sense lines). It is advantageous to very rapidly bring the potential of the node to the low value in order to reduce the time for the sense amplifier to detect the differential in potential levels of the digit and digit* lines.
In one prior art technique, the sense amplifier was strobed to a ground potential and the substrate was pumped to -2.5 V with respect to ground. The pumping of V.sub.SS to -2.5 V resulted in current consumption which would have been unnecessary if substrate was set to be equal to ground.
If the sense amplifier node were connected through an electrical device to ground, such as a diode, then the sense amplifier node would go in potential to a level of ground plus V.sub.T of the electrical device with the substrate grounded. This achieves the same effect as the case where the substrate is pumped to 2.5 V. As the potential of the node approached ground plus V.sub.T, the change in potential would tend to slow, resulting in the potential of the node hyperbolically approaching ground plus V.sub.T. On the other hand, if the node was connected by a transistor to ground, then the potential of the node would rapidly drop past the desired ground plus V.sub.T and settle at ground potential. It would be desirable to have the potential of the node drop rapidly, as in the case of a transistor connection, but settle at a potential of ground plus V.sub.T. Although an electrical device having a high threshold voltage reduces leakage current by increasing the potential of the sense node, it also reduces the high logic level that can written back to the cell.
U.S. Pat. No. 4,897,568, Active Up-Pump for Semiconductor Sense Lines, describes circuitry achieving an initial rapid drop in potential at the sense node with the sense node settling at a potential of ground plus V.sub.T. The circuitry described in U.S. Pat. No. 4,897,568 allows the sense node to be charged to V.sub.CC /2 during a precharge cycle for equilibration of the digit lines.
If the equilibration potential is reduced it follows that the minimum high level voltage parameter of the high logic state may also be reduced proportionally. Input data of a lower potential will be perceived as a relative high when compared to the lower equilibration potential. Thus potentials that were a marginally high logic state for an equilibration potential of V.sub.CC /2 are seen as a high logic state when the equilibration potential is less than V.sub.CC /2.
By widening the "high logic window" the reliability of the device is increased. The "high logic window" is the range of potentials which appear as a high logic level to a memory device. The window is defined by minimum and maximum voltage parameters of the high logic signal.
The cell signal is defined as the potential stored on the memory storage capacitor of a memory device. The cell margin is defined as the difference in potential between the cell signal and the potential of the digit/digit* lines of the memory device. The cell margin can be increased by retaining a given cell signal and decreasing the equilibrate potential of the digit lines. A larger cell margin increases the reliability of a memory device and reduces the soft error rate (SER). The SER is the number of errors experienced by a memory device during a fixed unit of time due to factors other than the memory device itself. The most common factor causing soft error is radiation.